The present invention relates to a heterojunction field-effect transistor.
A heterojunction field-effect transistor is one of various types of conventionally developed high-speed transistors.
This conventional heterojunction field-effect transistor has, for example, an arrangement as shown in FIG. 9.
Referring to FIG. 9, this transistor employs a semi-insulating semiconductor substrate 1 consisting of a compound semiconductor such as InP, and a buffer semiconductor layer 2, which consists of a compound semiconductor such as InAlAs and is intentionally not doped with either an n- or p-type impurity or is doped with either impurity at only a sufficiently low concentration, is formed on the semiconductor substrate 1. A channel formation semiconductor layer 3, which consists of a compound semiconductor such as InGaAs having electron affinity larger than that of the buffer semiconductor layer 2 and is intentionally not doped with either an n- or p-type impurity or is doped with either impurity at only a sufficiently low concentration, is formed on the buffer semiconductor layer 2.
An electron supply semiconductor layer 5, which consists of a compound semiconductor such as InAlAs having electron affinity smaller than that of the channel formation semiconductor layer 3 and is doped with an n-type impurity at a high concentration, is formed on the channel formation semiconductor layer 3 via a spacer semiconductor layer 4. The spacer semiconductor layer 4 consists of a compound semiconductor such as InAlAs having electron affinity smaller than that of the channel formation semiconductor layer 3, and is intentionally not doped with either an n- or p-type impurity or is doped with either impurity at only a sufficiently low concentration.
An electrode mounting semiconductor layer 6, which consists of a compound semiconductor such as InGaAs and is doped with an n-type impurity at a high concentration, is formed on the electron supply semiconductor layer 5. A window 7 for externally exposing the electron supply semiconductor layer 5 is formed in the electrode mounting semiconductor layer 6.
A gate electrode 8 is arranged on a region of the electron supply semiconductor layer 5, which corresponds to the window 7 of the electrode mounting semiconductor layer 6, so as to form a Schottky junction 9. On the electrode mounting semiconductor layer 6, a source electrode 10 and a drain electrode 11 are arranged on the left and right sides of the window 7 and therefore the gate electrode 8 so as to be in ohmic contact with the electrode mounting semiconductor layer 6.
According to the conventional heterojunction field-effect transistor having the above arrangement, electrons are supplied from the electron supply semiconductor layer 5 to the channel formation semiconductor layer 3 through the spacer semiconductor layer 4, so that an electron gas layer 13 is formed in a region of the channel formation semiconductor layer 3, which is located on the side of the spacer semiconductor layer 4.
When a control voltage is applied to the gate electrode 8 with respect to the source electrode 10 such that the voltage is superposed on a bias voltage sufficient to allow a depletion layer to expand from the Schottky junction 9 toward the semi-insulating semiconductor substrate 1 to reach or almost reach the heterojunction between the spacer semiconductor layer 4 and the channel formation semiconductor layer 3, the concentration of electrons in the channel formation semiconductor layer 3 according to electrons in the electron gas layer 13 is controlled in accordance with the value of the control voltage.
By, therefore, connecting a predetermined power source having a positive terminal on the drain electrode 11 side between the source electrode 10 and the drain electrode 11 via a load, a current corresponding to the control voltage can be supplied to the load to realize the function as a field-effect transistor.
In the conventional heterojunction field-effect transistor as shown in FIG. 9, however, since only one electron gas layer 13 is formed in the channel formation semiconductor layer 3 upon supply of electrons from the electron supply semiconductor layer 5, an average electron concentration in the channel formation semiconductor layer 3 cannot be sufficiently increased. Therefore, a current value to be supplied to the load cannot be increased.
In addition, when the conventional heterojunction field-effect transistor as shown in FIG. 9 achieves the function as a field-effect transistor described above, the field strength in a region of the channel formation semiconductor layer 3, which is located below the gate electrode 8, gradually increases from the end of the region located on the side of a region below the source electrode 10 toward its other end located on the side of a region below the drain electrode 11. However, in a compound semiconductor such as InGaAs constituting the channel formation semiconductor layer 3, the velocity of electrons which transit in the semiconductor shows a field strength dependency having a maximum value at a lower field strength position, as shown in FIG. 3. Therefore, a comparatively high electron velocity can be obtained in the portion of the region of the channel formation semiconductor layer 3, which is located below the gate electrode 8 and on the side of the region below the source electrode 10, whereas only a comparatively low electron velocity can be obtained in the portion of the region of the channel formation semiconductor layer 3, which is located below the gate electrode 8 and on the side of the region below the drain electrode 11. For this reason, the average velocity of electrons transiting in the channel formation semiconductor layer 3 is comparatively low. As a result, no good high-frequency characteristics as a field-effect transistor can be obtained.
Furthermore, in the conventional heterojunction field-effect transistor shown in FIG. 9, a narrow gap 12 is generally formed between the gate electrode 8 and the electrode mounting semiconductor layer 6 for the following reason. That is, a portion of the gate electrode 8, which is in direct contact with the electrode mounting semiconductor layer 6 doped with an n-type impurity at a high concentration, exhibits not Schottky characteristics but ohmic characteristics. Therefore, a gate leakage current flows directly from the gate electrode 8 to the electrode mounting semiconductor layer 6 to make it impossible to control the two-dimensional electron gas 13 in the channel formation semiconductor layer 3. The gap 12 is formed to avoid this inconvenience. However, the surface potential of the gap 12 easily changes because it is exposed to the atmosphere, chemicals, a plasma, and the like during the manufacture of a heterojunction field-effect transistor. In addition, the presence of the gap 12 allows the depletion layer below the gate electrode 8 to expand to a region below the gap 12, thereby reducing the concentration of the two-dimensional electron gas 13 in a region of the channel formation semiconductor layer 3 below the gap 12. This increases the source resistance and the drain resistance of the heterojunction field-effect transistor to significantly degrade its device characteristics. A degree of this reduction largely varies in accordance with the manufacturing steps of a heterojunction field-effect transistor, or the reduction significantly degrades stability of the device characteristics even after the transistor is manufactured.
The conventional heterojunction field-effect transistor shown in FIG. 9 must have a threshold voltage V.sub.th determined by the type of a circuit using this heterojunction field-effect transistor. When this threshold voltage is applied to the gate electrode 8 with respect to the source electrode 10, a field strength E.sub.s in the Schottky junction 9 is given by E.sub.s =2(V.sub.bi -V.sub.th)/d where d is the thickness of the electron supply semiconductor layer 5 and V.sub.bi is the built-in potential present in the electron supply semiconductor layer 5, the spacer semiconductor layer 4, and the channel formation semiconductor layer 3. In order to ensure the breakdown voltage of the gate electrode, E.sub.s must be decreased to be a predetermined value or less, which is determined by a semiconductor material concerned. As is apparent from the equation stated above, since E.sub.s is determined by only d provided that V.sub.th is fixed, d cannot be decreased. However, a transconductance g.sub.m of the transistor is given by g.sub.m =.epsilon.V.sub.s /d (V.sub.s =electron velocity), and it is impossible to increase the transconductance. Therefore, it is difficult to improve the characteristics of the transistor while ensuring the gate breakdown voltage.